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PRELIMINARY
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
ICS853052
GENERAL DESCRIPTION
The ICS853052 is a Dual LVCMOS / LVTTL-toIC S Differential 2.5V, 3.3V, 5V LVPECL Multiplexer and HiPerClockSTM a member of the HiPerClocksTM family of High Perfor mance Clocks Solutions from IDT. The ICS853052 has two selectable single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translates them to 2.5V, 3.3V or 5V LVPECL levels. The small outline 8-pin TSSOP or 8-pin SOIC packages make this device ideal for applications where space, high performance and low power are important.
FEATURES
* One differential 2.5V, 3.3V or 5V LVPECL output * Two selectable LVCMOS/LVTTL clock inputs * Output frequency: TBD * Additive phase jitter, RMS: 0.06ps (typical) * Propagation Delay: 370ps (typical) * 2.5V, 3.3V or 5V operating supply voltage (operating range 2.375V to 5.5V) * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
BLOCK DIAGRAM
PIN ASSIGNMENT
nc Da Db SEL
Q nQ
Da Pulldown
1
1 2 3 4
8 7 6 5
VCC Q nQ VEE
ICS853052
8-Lead TSSOP, 118 mil 3mm x 3mm x 0.95mm package body G Package Top View 8-Lead SOIC, 150 mil 3.90mm x 4.90mm x 1.37mm package body M Package Top View
Db Pulldown
0
SEL Pulldown
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3 4 5 6, 7 8 Name nc Da, Db SEL VEE nQ, Q VCC Input Input Power Output Power Type Unused Description No connect. Pulldown LVCMOS / LVTTL clock inputs. Select input pin. When HIGH, selects Da input clock. Pulldown When Low selects Db input clock. Single-ended 100H LVPECL interface levels. Negative supply pin. Differential output pair. LVPECL interface levels. Positive supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 1 75 Maximum Units pF k
TABLE 3.
SEL 0 1
CONTROL INPUT FUNCTION TABLE
Inputs Selected Source Db Da
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052 DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 6V (LVPECL mode, VEE = 0) -6V (ECL mode, VCC = 0) -0.5V to VCC + 0.5 V 0.5V to VEE - 0.5V 50mA 100mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Temperature Range, TA -40C to +85C Package Thermal Impedance, JA 101.7C/W (0 m/s) TSSOP (Junction-to-Ambient) 112.7C/W (0 lfpm) SOIC
TABLE 4A. DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol IEE VOH VOL VIH VIL IIH Parameter Power Supply Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended Input Low Voltage, Single-Ended Input High Current 1.375 0.605 1.275 0.63 Min -40C Typ 21 1.475 0.745 1.58 0.88 1.56 0.965 200 200 1.425 0.625 1.275 0.63 Ma x Min 25C Typ 21 1.495 0.72 1.57 0.815 1.56 0.965 200 200 1.495 0.64 1.275 0.63 Max Min 85C Typ 21 1.53 0.735 1.565 0.83 -0.83 0.965 200 Max Units mA
V V V V
A A
Input Low Current 200 IIL Input and output parameters var y 1:1 with VCC. NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 4B. DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol Parameter IEE V OH V OL VIH VIL IIH Power Supply Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended Input Low Voltage, Single-Ended Input High Current 2175 1405 2075 1355 Min -40C Typ 21 2275 1545 2380 1680 2420 1675 200 20 0 2225 1425 2075 1355 Max Min 25C Typ 21 2295 1520 2370 1615 2420 1675 200 200 2295 1440 2075 1355 Max Min 85C Typ 21 2330 1535 2365 1630 2420 1675 200 Max Units mA mV mV mV mV A A
IIL Input Low Current 200 Input and output parameters vary 1:1 with VCC. NOTE 1: Outputs terminated with 50 to VCC - 2V.
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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PRELIMINARY
TABLE 4C. DC CHARACTERISTICS, VCC = 5V; VEE = 0V
Symbol IEE VOH VOL VIH VIL IIH Parameter Power Supply Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended Input Low Voltage, Single-Ended Input High Current 3875 3105 3775 3055 200 200 Min -40C Typ 21 3975 3245 4105 3380 4120 3375 4080 3125 3775 3055 200 Max Min 25C Typ 21 3925 3220 3995 3315 4120 3375 4070 3140 3775 3055 200 200 Max Min 85C Typ 21 3995 3235 4065 3330 4120 3375 200 Max Units mA mV mV mV mV A A
Input Low Current IIL Input and output parameters vary 1:1 with VCC. NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -2.375V
Symbol IEE VOH VOL VIH VIL IIH Parameter Power Supply Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended Input Low Voltage, Single-Ended Input High Current -1125 -1895 -1225 -1945 Min -40C Typ 21 -1025 -1755 -920 -1620 -880 -1625 200 200 -1075 -1875 -1225 -1945 Max Min 25C Typ 21 -1005 -1780 -930 -1685 -880 -1625 200 200 -1005 -1860 -1225 -1945 Max Min 85C Typ 21 -970 -1765 -935 -1670 -880 -1625 200 Max Units mA mV mV mV mV A A
Input Low Current 200 IIL Input and output parameters vary 1:1 with VCC. NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -2.375V OR VCC = 2.375V TO 5.5V; VEE = 0V
Symbol fMAX Parameter -40C Min Typ Max Min 25C Typ Max Min 85C Typ TBD TBD TBD TBD TBD TBD Max Units GHz ps ps ps ps ps
Output Frequency TBD TBD Propagation Delay, Low to High; t PLH TBD 370 NOTE 1 Propagation Delay, High to Low; TBD 370 t PHL NOTE 1 Buffer Additive Phase Jitter, TBD 0.06 t jit RMS; refer to Additive Phase Jitter section V PP Input Voltage Swing (Differential) TBD TBD Output tR/tF 20% to 80% TBD 180 Rise/Fall Time All parameters are measured 1GHz unless otherwise noted. NOTE 1: Measured from VCC/2 of the input crossing point to the differential output crossing point.
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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PRELIMINARY
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz
0 -10 -20 -30 -40 -50
band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz
(12kHz to 20MHz) = 0.06ps typical
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 100 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
Da Db nQ
LVPECL
nQx VEE
Q
tPD
-3.5V to -0.375V
OUTPUT LOAD AC TEST CIRCUIT
PROPAGATION DELAY
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052 DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS:
DX INPUTS For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the Dx input to ground.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 1A and Figure 1B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 1B can be eliminated and the termination is shown in Figure 1C.
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 1A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 1B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 1C. 2.5V LVPECL TERMINATION EXAMPLE
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052 DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termination. Figure 3A shows standard termination for 5V LVPECL. The termination requires matched load of 50 resistors pull down to V CC - 2V = 3V at the receiver. Figure 3B shows Thevenin equivalence of Figure 3A. In actual application where the 3V DC power supply is not available, this approached is normally used.
5V
5V 5V PECL Zo = 50 Ohm + Zo = 50 Ohm PECL
R1 125 R2 125 Zo = 50 Ohm PECL 5V R3 84 PECL Zo = 50 Ohm + R4 84
R1 50 3V
R2 50
FIGURE 3A. STANDARD 5V LVPECL OUTPUT TERMINATION
FIGURE 3B. 5V LVPECL OUTPUT TERMINATION EXAMPLE
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052 DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853052. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853052 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 5.5V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 5.5V * 21mA = 115.5mW Power (outputs)MAX = 30.94mW/Loaded Output pair
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 112.7C/W per Table 6B below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.146W * 112.7C/W = 101.52C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE JA
FOR
8-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2
89.8C/W
TABLE 6B. THERMAL RESISTANCE JA
FOR
8-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052 DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50 VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = VOH_MAX = VCC_MAX - 0.935V (VCC_MAX - VOH_MAX) = 0.935V
*
For logic low, VOUT = VOL_MAX = VCC_MAX - 1.67V (VCC_MAX - VOL_MAX) = 1.67V
Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V
L
CC_MAX
- VOH_MAX))/R ] * (VCC _MAX- VOH_MAX) =
L
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) = [(2V - (V
L
CC_MAX
- VOL_MAX))/R ] * (VCC_MAX - VOL_MAX) =
L
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 7A. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2
89.8C/W
TABLE 7B. JAVS. AIR FLOW TABLE
FOR
8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853052 is: 110 Pin compatible with MC100EP58
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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PRELIMINARY
PACKAGE OUTLINE - G SUFFIX
FOR
8 LEAD TSSOP
PACKAGE OUTLINE - M SUFFIX
FOR
8 LEAD SOIC
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e e1 L aaa 0.40 0 --0 0.79 0.22 0.08 3.00 BASIC 4.90 BASIC 3.00 BASIC 0.65 BASIC 1.95 BASIC 0.80 8 0.10 Millimeters Minimum 8 1.10 0.15 0.97 0.38 0.23 Maximum
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-187
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PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS853052AG ICS853052AGT ICS853052AGLF ICS853052AGLFT ICS853052AM ICS853052AMT ICS853052AMLF ICS853052AMLFT Marking 052A 052A 52AL 52AL 853052A 853052A TBD TBD Package 8 lead TSSOP 8 lead TSSOP 8 lead "Lead-Free" TSSOP 8 lead "Lead-Free" TSSOP 8 lead SOIC 8 lead SOIC 8 lead "Lead-Free" SOIC 8 lead "Lead-Free" SOIC Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C
Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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PRELIMINARY
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www.IDT.com
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Corporate Headquarters
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Asia Pacific and Japan
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Europe
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(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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